1. Field of the Invention
The present invention relates to a method for producing a semiconductor device, and more particularly to such method enabling satisfactory alignment of a pattern formed after gaseous crystal growth with a pattern formed before gaseous crystal growth.
2. Related Background Art
FIG. 1 shows an example of a stepped pattern formation on a semiconductor substrate.
At first, on a surface with an orientation (100) of a p-type semiconductor (Si) substrate 1 of a specific resistivity of 10-20 .OMEGA..multidot.cm, a SiO.sub.2 film 2 of a thickness of 0.5-2.0 .mu.m is formed over the entire area, and a photoresist layer is formed thereon. Then said photoresist layer is patterned to obtain a mask pattern, and the thus exposed portion of the SiO.sub.2 film 2 is removed with HF wet etching, whereby an aperture 3 is formed in the SiO.sub.2 film 2 at a desired position for forming an embedded layer as shown in FIG. 1A.
Then, in order to obtain n-type conductivity, the semiconductor substrate 1 is subjected, in the exposed surface thereof, to doping by implantation of As ions as impurity component, and then to heat treatment in an oxidative atmosphere. The ion implantation is conducted with a dose of 1.times.10.sup.14 -1.times.10.sup.16 /cm.sup.2 and an accelerating voltage of 30-90 keV, while the heat treatment is conducted at a temperature of 900.degree. -1200.degree. C. Thus, as shown in FIG. 1B, the exposed surface of the semiconductor substrate 1 is oxidized as a new SiO.sub.2 film 4, and a high impurity concentration area 5 is formed thereunder.
Then said SiO.sub.2 films 2 and 4 are removed by HF wet etching, whereby, as shown in FIG. 1C, a step 6 is formed on the surface of the semiconductor substrate 1, at the boundary between said high impurity concentration area 5 and the other area.
Subsequently, gaseous crystal growth is conducted over the entire surface, with gasses of SiHCl.sub.3, SiCl.sub.4 or SiH.sub.2 Cl.sub.2 ; a temperature of 950.degree. C.-1150.degree. C., a pressure from atmospheric pressure to 50 Torr and a growth speed of 0.1 to 1.5 .mu.m/min. whereby a gaseous grown crystal layer 7, formed by epitaxial growth, is formed on the semiconductor substrate as shown in FIG. 1D. The surface of said crystal layer has a step 8 corresponding to the step 6 on the surface of said substrate 1.
Therefore, an embedded layer of low resistivity is formed in this manner, composed of the high impurity concentration area 5. Said embedded layer, used for example for reducing the collector resistance of a transistor, is formed with a low resistance and with a conductive type same as that of a crystalline layer formed by gaseous crystal growth on the surface of the semiconductor substrate.
Any process to be applied to the semiconductor substrate having such embedded layer 5 formed therein should be well aligned with the pattern of said embedded layer which corresponds to the pattern of the step 6. Said alignment can be made with reference to the pattern of the step 8 on the surface of the gaseous grown crystal layer, which corresponds to the pattern of the step 6 of the embedded layer 5, said step 6 being formed for the purpose of alignment simultaneously with said embedded layer 5.
The manufacturing process of semiconductor devices as explained above is generally conducted with reference to an orientation flat formed on the semiconductor substrate. The alignment pattern is formed diagonally with respect to a normal line to said orientation flat.
FIG. 2A is a plan view of a state shown in FIG. 1C, and FIGS. 2B and 2C are plan views of a state shown in FIG. 1D.
Conventionally, the orientation flat 10 of a Si substrate 1 is formed as a (110) surface as shown in FIG. 2. There are shown stepped patterns 6a, 6b of a functional part, such as a resistor, a PN junction capacitor, a bipolar transistor or a MOS transistor of a semiconductor device; and a stepped pattern for alignment. Said pattern 6c is L-shaped composed of two linear portions positioned at 45.degree. to the normal line to the orientation flat 10.
In the gaseous crystal growth, the pattern growth is faster in the direction [100] or [010]. The growth speed in either of said two directions becomes larger, depending upon the growth conditions. If the growth speed is larger in a direction A shown in FIG. 2B, with the gaseous growth of the crystal layer 7, the pattern width of the functional part scarcely changes so that the steps 8a, 8b formed on the surface of the crystal layer 7 at the end of the aforementioned steps 6a, 6b. However, the width of one of linear portions of the alignment pattern increases gradually, so that the step 8c formed on the surface of said crystal layer 7 does not exactly correspond to said step 6c at the end of the gaseous crystal growth. A similar situation occurs in case the crystal growth is faster in a direction B as shown in FIG. 2C.
In the conventional method, therefore, a sufficiently high precision of alignment is difficult to achieve, because the alignment pattern changes the form by the gaseous crystal growth.
Because recent semiconductor manufacturing apparatus perform alignment automatically, the above-mentioned change in the alignment pattern may disturb the function of said apparatus. Such a situation not only lowers the yield of the semiconductor devices to be produced but also exerts great influence on the mass production, elevating the cost thereof. The above-mentioned technical problem has to be solved in order to achieve commercial success in the production.